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Assertions (and their exclusive inputs) should be guarded by `ifdefs #1942

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grebe opened this issue Feb 20, 2025 · 1 comment
Open

Assertions (and their exclusive inputs) should be guarded by `ifdefs #1942

grebe opened this issue Feb 20, 2025 · 1 comment
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codegen Related to emitting (System)Verilog.

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grebe commented Feb 20, 2025

Our assertions should be guarded by `ifdef guards. This allows users to easily disable assertions without a recompile and also prevents assertions from being visible to synthesis- I believe yosys in particular can leave in stuff that causes problems for openroad if assertions aren't stripped.

Ideally, we'd also guard all the wires/regs that only feed assertions (or other wires/regs that only feed assertions) in those same guards to avoid "value not read" issues.
@grebe grebe added the codegen Related to emitting (System)Verilog. label Feb 20, 2025
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grebe commented Feb 20, 2025

Related: #1048

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codegen Related to emitting (System)Verilog.
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